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eorex em488m3244vba jul. 2006 www.eorex.com 1/17 256mb (2m 4bank 32) synchronous dram features ? fully synchronous to positive clock edge ? single 3.3v 0.3v power supply ? lvttl compatible with multiplexed address ? programmable burst length (b/l) - 1, 2, 4, 8 or full page ? programmable cas latency (c/l) - 2 or 3 ? data mask (dqm) for read / write masking ? programmable wrap sequence C sequential (b/l = 1/2/4/8/full page) C interleave (b/l = 1/2/4/8) ? burst read with single-bit write operation ? all inputs are sampled at the rising edge of the system clock ? auto refresh and self refresh ? 4,096 refresh cycles / 64ms (15.625us) description the em488m3244vba is synchronous dynamic random access memory (sdram) organized as 2meg words x 4 banks by 32 bits. all inputs and outputs are synchronized with the positive edge of the clock. the 256mb sdram uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 3.3v low power memory system. it also provides auto refresh with power saving / down mode. all inputs and outputs voltage levels are compatible with lvttl. available packages: tfbga-90b(13mmx8mm). ordering information part no organization max. freq package grade pb em488m3244vba-75f 8m x 32 133mhz @cl3 tfbga -90b commercial free * eorex reserves the right to change products or specification without notice.
eorex em488m3244vba jul. 2006 www.eorex.com 2/17 pin assignment 1 2 3 7 8 9 dq26 dq24 vss a vdd dq23 dq21 dq28 vddq vssq b vddq vssq dq19 vssq dq27 dq25 c dq22 dq20 vddq vssq dq29 dq30 d dq17 dq18 vddq vddq dq31 nc e nc dq16 vssq vss dqm3 a3 f a2 dqm2 vdd a4 a5 a6 g a10 a0 a1 a7 a8 nc h nc ba1 a11 clk cke a9 j ba0 /cs /ras dqm1 nc nc k /cas /we dqm0 vddq dq8 vss l vdd dq7 vssq vssq dq10 dq9 m dq6 dq5 vddq vssq dq12 dq14 n dq1 dq3 vddq dq11 vddq vssq p vddq vssq dq4 dq13 dq15 vss r vdd dq0 dq2 90ball tfbga / (13mm x 8mm)
eorex em488m3244vba jul. 2006 www.eorex.com 3/17 pin description (simplified) pin name function j1 clk (system clock) master clock input (active on the positive rising edge) j8 /cs (chip select) selects chip when active j2 cke (clock enable) activates the clk when h and deactivates when l . cke should be enabled at least one cycle prior to new command. disable input buffers for power down in standby. g8,g9,f7,f3,g1, g2,g3,h1,h2,j3, g7,h9 a0~a11 (address) row address (a0 to a11) is determined by a0 to a11 level at the bank active command cycle clk rising edge. ca (ca0 to ca8) is determined by a0 to a8 level at the read or write command cycle clk rising edge. and this column address becomes burst access start address. a10 defines the pre-charge mode. when a10= high at the pre-charge command cycle, all banks are pre-charged. but when a10= low at the pre-charge command cycle, only the bank that is selected by ba is pre-charged. j7,h8 ba0,ba1 (bank address) selects which bank is to be active. j9 /ras (row address strobe) latches row addresses on the positive rising edge of the clk with /ras l . enables row access & pre-charge. k7 /cas (column address strobe) latches column addresses on the positive rising edge of the clk with /cas low. enables column access. k8 /we (write enable) latches column addresses on the positive rising edge of the clk with /cas low. enables column access. k9,k1,f8,f2 dqm0~dqm3 (data input/output mask) dqm controls i/o buffers. r8,n7,r9,n8,p9, m8,m7,l8,l2,m3, m2,p1,n2,r1,n3, r2,e8,d7,d8,b9, c8,a9,c7,a8,a2, c3,a1,c2,b1,d2, d3,e2 dq0~dq31 (data input/output) dq pins have the same function as i/o pins on a conventional dram. a7,f9,l7,r7/ a3,f1,l3,r3 v dd /v ss (power supply/ground) v dd and v ss are power supply pins for internal circuits. b2,b7,c9,d9,e1, l1,m9,n9,p2/b8, b3,c1,d1,e9,l9, m1,n1,p8 v ddq /v ssq (power supply/ground) v ddq and v ssq are power supply pins for the output buffers. e3,e7,h3,h7,k2, k3 nc (no connection) this pin is recommended to be left no connection on the device.
eorex em488m3244vba jul. 2006 www.eorex.com 4/17 absolute maximum rating symbol item rating units v in , v out input, output voltage -0.5 ~ +4.6 v v dd , v ddq power supply voltage -0.5 ~ +4.6 v commercial 0 ~ +70 t op operating temperature range extended -25 ~ +85 c t stg storage temperature range -55 ~ +150 c p d power dissipation 1 w i os short circuit current 50 ma note: caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. capacitance (v cc =3.3v, f=1mhz, t a =25 c) symbol parameter min. typ. max. units c clk clock capacitance 1.5 3.0 pf c i input capacitance for clk, cke, address, /cs, /ras, /cas, /we, dqml, dqmu 1.5 3.0 pf c o input/output capacitance 3.0 5.5 pf recommended dc operating conditions (t a =0 c ~70 c) symbol parameter min. typ. max. units v dd power supply voltage 3.0 3.3 3.6 v v ddq power supply voltage (for i/o buffer) 3.0 3.3 3.6 v v ih input logic high voltage 2.0 v dd +0.3 v v il input logic low voltage -0.3 0.8 v note: * all voltages referred to v ss . * v ih (max.) = vdd+1.5v for pulse width 5ns * v il (min.) = vss-1.5v for pulse width 5ns
eorex em488m3244vba jul. 2006 www.eorex.com 5/17 recommended dc operating conditions (v dd =3.3v 0.3v, t a =0 c ~70 c) symbol parameter test conditions max. units i cc1 operating current (note 1) burst length=1, t rc 3 t rc (min.), i ol =0ma, one bank active 125 ma i cc2p cke v il (max.), t ck =15ns 3 ma i cc2ps precharge standby current in power down mode cke v il (max.), t ck = 2 ma i cc2n cke 3 v il (min.), t ck =15ns, /cs 3 v ih (min.) input signals are changed one time during 30ns 20 ma i cc2ns precharge standby current in non-power down mode cke 3 v il (min.), t ck = , input signals are stable 9 ma i cc3p cke v il (max.), t ck =15ns 4 ma i cc3ps active standby current in power down mode cke v il (max.), t ck = 3 ma i cc3n cke 3 v il (min.), t ck =15ns, /cs 3 v ih (min.) input signals are changed one time during 30ns 45 ma i cc3ns active standby current in non-power down mode cke 3 v il (min.), t ck = , input signals are stable 30 ma i cc4 operating current (burst mode) (note 2) t ccd 3 2clks, i ol =0ma 150 ma i cc5 refresh current (note 3) t rc 3 t rc (min.) 270 ma i cc6 self refresh current cke 0.2v 3 (note 4) ma *all voltages referenced to v ss . note 1: i cc1 depends on output loading and cycle rates. specified values are obtained with the output open. input signals are changed only one time during t ck (min.) note 2: i cc4 depends on output loading and cycle rates. specified values are obtained with the output open. input signals are changed only one time during t ck (min.) note 3: input signals are changed only one time during t ck (min.) note 4: standard power version. recommended dc operating conditions (continued) symbol parameter test conditions min. typ. max. units i il input leakage current 0 v i v ddq , v ddq =v dd all other pins not under test=0v -1 +1 ua i ol output leakage current 0 v o v ddq , d out is disabled -1.5 +1.5 ua v oh high level output voltage i o =-2ma 2.4 v v ol low level output voltage i o =+2ma 0.4 v
eorex em488m3244vba jul. 2006 www.eorex.com 6/17 block diagram r o w a d d . b u f f e r r o w d e c o d e r a d d r e s s r e g i s t e r auto/self refresh counter memory array s/a & i/o gating col. decoder col. add. buffer mode register set col. add. counter burst counter read dqm control write dqm control data in data out doi a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 ba0 ba1 timing register clkcke/cs/ras/cas/wedqm dqm
eorex em488m3244vba jul. 2006 www.eorex.com 7/17 ac operating test conditions (v dd =3.3v 0.3v, t a =0 c ~70 c) item conditions output reference level 1.4v/1.4v output load see diagram as below input signal level 2.4v/0.4v transition time of input signals 2ns input reference level 1.4v ac operating test characteristics (v dd =3.3v 0.3v, t a =0 c ~70 c) -75 symbol parameter min. max. units cl=3 7 t ck clock cycle time cl=2 10 ns cl=3 5.4 t ac access time form clk cl=2 5.4 ns t ch clk high level width 2.5 ns t cl clk low level width 2.5 ns cl=3 2 t oh data-out hold time cl=2 2 ns cl=3 5.4 t hz data-out high impedance time (note 5) cl=2 5.4 ns t lz data-out low impedance time 0 ns t ih input hold time 0.8 ns t is input setup time 1.5 ns * all voltages referenced to v ss . note 5: t hz defines the time at which the output achieve the open circuit condition and is not referenced to output voltage levels.
eorex em488m3244vba jul. 2006 www.eorex.com 8/17 ac operating test characteristics (continued) (v dd =3.3v 0.3v, t a =0 c ~70 c) -75 symbol parameter min. max. units t rc active to active command period (note 6) 67.5 ns t ras active to precharge command period (note 6) 45 120k ns t rp precharge to active command period (note 6) 20 ns t rcd active to read/write delay time (note 6) 20 ns t rrd active(one) to active(another) command (note 6) 15 ns t ccd read/write command to read/write command 1 clk t dpl date-in to precharge command 2 clk t bdl date-in to burst stop command 1 clk cl=3 3 t roh data-out to high impedance from precharge command cl=2 2 clk t ref refresh time (4,096 cycle) 64 ms * all voltages referenced to v ss . note 6: these parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing/clock period (count fractions as a whole number) recommended power on and initialization the following power on and initialization sequence guarantees the device is preconditioned to each user s specific needs. (like a conventional dram) during power on, all v dd and v ddq pins must be built up simultaneously to the specified voltage when the input signals are held in the nop state. the power on voltage must not exceed v dd +0.3v on any of the input pins or v dd supplies. (clk signal started at same time) after power on, an initial pause of 200 s is required followed by a precharge of all banks using the precharge command. to prevent data contention on the dq bus during power on, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode register set command must be issued to initialize the mode register. a minimum of eight auto refresh cycles (cbr) are also required, and these may be done before or after programming the mode register.
eorex em488m3244vba jul. 2006 www.eorex.com 9/17 simplified state diagram read read suspend write writea precharge reada suspend reada row active idle self refresh cbr refresh mode register set active power down write suspend writea suspend power on power down cke cke cke cke precharge c k e c k e s e l f s e l f e x i t ref mrs cke cke cke cke cke cke writeread read r e a d b s t write manual input automatic sequence
eorex em488m3244vba jul. 2006 www.eorex.com 10/17 address input for mode register set ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 operation mode cas latency bt burst length burst length sequential interleave a2 a1 a0 1 1 0 0 0 2 2 0 0 1 4 4 0 1 0 8 8 0 1 1 reserved reserved 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 full page reserved 1 1 1 burst type a3 interleave 1 sequential 0 cas latency a6 a5 a4 reserved 0 0 0 reserved 0 0 1 2 0 1 0 3 0 1 1 reserved 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 ba1 ba0 a11 a10 a9 a8 a7 operation mode 0 0 0 0 0 0 0 normal 0 0 0 0 1 0 0 burst read with single-bit write
eorex em488m3244vba jul. 2006 www.eorex.com 11/17 burst type (a3) burst length a2 a1 a0 sequential addressing interleave addressing x x 0 0 1 0 1 2 x x 0 1 0 1 0 x 0 0 0 1 2 3 0 1 2 3 x 0 1 1 2 3 0 1 0 3 2 x 1 0 2 3 0 1 2 3 0 1 4 x 1 1 3 0 1 2 3 2 1 0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 8 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 full page* n n n cn cn+1 cn+2 - * page length is a function of i/o organization and column addressing 32 (ca0 ~ ca8): full page = 512bits 1. command truth table cke command symbol n-1 n /cs /ras /cas /we ba0, ba1 a10 a11, a9~a10 ignore command desl h x h x x x x x x no operation nop h x l h h h x x x burst stop bsth h x l h h l x x x read read h x l h l h v l v read with auto pre-charge reada h x l h l h v h v write writ h x l h l l v l v write with auto pre-charge writa h x l l h h v h v bank activate act h x l l h h v v v pre-charge select bank pre h x l l h l v l x pre-charge all banks pall h x l l h l x h x mode register set mrs h x l l l l l l v h = high level, l = low level, x = high or low level (don't care), v = valid data input
eorex em488m3244vba jul. 2006 www.eorex.com 12/17 2. dqm truth table cke command symbol n-1 n /cs data write/output enable enb h x h data mask/output disable mask h x l upper byte write enable/output enable bsth h x l read read h x l read with auto pre-charge reada h x l write writ h x l write with auto pre-charge writa h x l bank activate act h x l pre-charge select bank pre h x l pre-charge all banks pall h x l mode register set mrs h x l h = high level, l = low level, x = high or low level (don't care), v = valid data input 3. cke truth table cke item command symbol n-1 n /cs /ras /cas /we addr. activating clock suspend mode entry h l x x x x x any clock suspend mode l l x x x x x clock suspend clock suspend mode exit l h x x x x x idle cbr refresh command ref h h l l l h x idle self refresh entry self h l l l l h x l h l h h h x self refresh self refresh exit l h h x x x x idle power down entry h l x x x x x power down power down exit l h x x x x x remark h = high level, l = low level, x = high or low level (don't care)
eorex em488m3244vba jul. 2006 www.eorex.com 13/17 4. operative command table (note 7) current state /cs /r /c /w addr. command action h x x x x desl nop or power down (note 8) l h h x x nop or bst nop or power down (note 8) l h l h ba/ca/a10 read/reada illegal (note 9) l h l l ba/ca/a10 writ/writa illegal (note 9) l l h h ba/ra act row activating l l h l ba, a10 pre/pall nop l l l h x ref/self refresh or self refresh (note 10) idle l l l l op-code mrs mode register accessing h x x x x desl nop l h h x x nop or bst nop l h l h ba/ca/a10 read/reada begin read: determine ap (note 11) l h l l ba/ca/a10 writ/writa begin write: determine ap (note 11) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall pre-charge (note 12) l l l h x ref/self illegal (note 10) row active l l l l op-code mrs illegal h x x x x desl continue burst to end ? row active l h h h x nop continue burst to end ? row active l h h l x bst burst stop ? row active l h l h ba/ca/a10 read/reada terminate burst, new read: determine ap (note 13) l l l l ba/ca/a10 writ/writa terminate burst, start write: determine ap (note 13, 14) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall terminate burst, pre-charging (note 10) l l l h x ref/self illegal read l l l l op-code mrs illegal h x x x x desl continue burst to end ? write recovering l h h h x nop continue burst to end ? write recovering l h h l x bst burst stop ? row active l h l h ba/ca/a10 read/reada terminate burst, start read: determine ap 7, 8 (note 13, 14) l l l l ba/ca/a10 writ/writa terminate burst, new write: determine ap 7 (note 13) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall terminate burst, pre-charging (note 15) l l l h x ref/self illegal write l l l l op-code mrs illegal remark h = high level, l = low level, x = high or low level (don't care)
eorex em488m3244vba jul. 2006 www.eorex.com 14/17 4. operative command table (continued) (note 7) current state /cs /r /c /w addr. command action h x x x x desl continue burst to end ? pre-charging l h h h x nop continue burst to end ? pre-charging l h h l x bst illegal l h l h ba/ca/a10 read/reada illegal (note 9) l h l l ba/ca/a10 writ/writa illegal (note 9) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall illegal (note 9) l l l h x ref/self illegal read with ap l l l l op-code mrs illegal h x x x x desl burst to end ? write recovering with auto pre-charge l h h h x nop continue burst to end ? write recovering with auto pre-charge l h h l x bst illegal l h l h ba/ca/a10 read/reada illegal (note 9) l h l l ba/ca/a10 writ/writa illegal (note 9) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall illegal (note 9) l l l h x ref/self illegal write with ap l l l l op-code mrs illegal h x x x x desl nop ? enter idle after t rp l h h h x nop nop ? enter idle after t rp l h h l x bst illegal l h l h ba/ca/a10 read/reada illegal (note 9) l h l l ba/ca/a10 writ/writa illegal (note 9) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall nop ? enter idle after t rp l l l h x ref/self illegal pre-charging l l l l op-code mrs illegal h x x x x desl nop ? enter idle after t rcd l h h h x nop nop ? enter idle after t rcd l h h l x bst illegal l h l h ba/ca/a10 read/reada illegal (note 9) l h l l ba/ca/a10 writ/writa illegal (note 9) l l h h ba/ra act illegal (note 9, 16) l l h l ba, a10 pre/pall illegal (note 9) l l l h x ref/self illegal row activating l l l l op-code mrs illegal remark h = high level, l = low level, x = high or low level (don't care), ap = auto pre-charge
eorex em488m3244vba jul. 2006 www.eorex.com 15/17 4. operative command table (continued) (note 7) current state /cs /r /c /w addr. command action h x x x x desl nop ? enter row active after t dpl l h h h x nop nop ? enter row active after t dpl l h h l x bst nop ? enter row active after t dpl l h l h ba/ca/a10 read/reada start read, determine ap l h l l ba/ca/a10 writ/writa new write, determine ap (note 14) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall illegal (note 9) l l l h x ref/self illegal write recovering l l l l op-code mrs illegal h x x x x desl nop ? enter pre-charge after t dpl l h h h x nop nop ? enter pre-charge after t dpl l h h l x bst nop ? enter pre-charge after t dpl l h l h ba/ca/a10 read/reada illegal (note 9, 14) l h l l ba/ca/a10 writ/writa illegal (note 9) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall illegal l l l h x ref/self illegal write recovering with ap l l l l op-code mrs illegal h x x x x desl nop ? enter idle after t rc l h h x x nop/bst nop ? enter idle after t rc l h l x x read/writ illegal l l h x x act/pre/pall illegal refreshing l l l x x ref/self/mrs illegal h x x x x desl nop l h h h x nop nop l h h l x bst illegal l h l x x read/writ illegal mode register accessing l l x x x act/pre/pall/ ref/self/mrs illegal remark h = high level, l = low level, x = high or low level (don't care), ap = auto pre-charge note 7: all entries assume that cke was active (high level) during the preceding clock cycle. note 8: if all banks are idle, and cke is inactive (low level), sdram will enter power down mode. all input buffers except cke will be disabled. note 9: illegal to bank in specified states; function may be legal in the bank indicated by bank address (ba), depending on the state of that bank. note 10: if all banks are idle, and cke is inactive (low level), sdram will enter self refresh mode. all input buffers except cke will be disabled. note 11: illegal if t rcd is not satisfied. note 12: illegal if t ras is not satisfied. note 13: must satisfy burst interrupt condition. note 14: must satisfy bus contention, bus turn around, and/or write recovery requirements. note 15: must mask preceding data which don't satisfy t dpl . note 16: illegal if t rrd is not satisfied.
eorex em488m3244vba jul. 2006 www.eorex.com 16/17 5. command truth table for cke cke current state n-1 n /cs /r /c /w addr. action h x x x x x x invalid, clk(n-1) would exit self refresh l h h x x x x self refresh recovery l h l h h x x self refresh recovery l h l h l x x illegal l h l l x x x illegal self refresh l l x x x x x maintain self refresh h h h x x x x idle after t rc h h l h h x x idle after t rc h h l h l x x illegal h h l l x x x illegal h l h x x x x illegal h l l h h x x illegal h l l h l x x illegal self refresh recovery h l l l x x x illegal h x x x x x x invalid, clk(n-1) would exit power down l h x x x x x exit power down ? idle power down l l x x x x x maintain power down mode h h h x x x h h l h x x h h l l h x refer to operations in operative command table h h l l l h x refresh h h l l l l op-code h l h x x x h l l h x x h l l l h x refer to operations in operative command table h l l l l h x self refresh (note 17) h l l l l l op-code refer to operations in operative command table both banks idle l x x x x x x power down (note 17) h x x x x x x refer to operations in operative command table row active l x x x x x x power down (note 17) h h x x x x refer to operations in operative command table h l x x x x x begin clock suspend next cycle (note 18) l h x x x x x exit clock suspend next cycle any state other than listed above l l x x x x x maintain clock suspend remark: h = high level, l = low level, x = high or low level (don't care) notes 17: self refresh can be entered only from the both banks idle state. power down can be entered only from both banks idle or row active state. notes 18: must be legal command as defined in operative command table
eorex em488m3244vba jul. 2006 www.eorex.com 17/17 package description

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